Non-volatile memory device and method of fabricating the same
US7812375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Jun 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/47
Abstract
In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.