High-voltage extended drain MOSFET
US7812393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Nov 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ “as-implanted” dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.