Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging

US7812438B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Virendra R. Jadhav · Wappingers Falls, US
• David L. Questad · Hopewell Junction, US
• Kamal K. Sikka · Poughkeepsie, US
• Xiaojin Wei · Poughkeepsie, US
• Jiantao Zheng · Hopewell Junction, US

Key dates

• Filing date: Jan 7, 2008
• Grant date: Oct 12, 2010
• Expiry date: May 6, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the BEOL. Tensile stress imposed on the via is reduced by shifting the via towards the center of a silicon chip or alternatively shifting the UBM towards the corners of the silicon chip.