Clock signal circuitry for multi-channel data signaling
US7812659B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2006 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Aug 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.