Non-linear conductor memory
US7813157B2 · kind B2 · utility
6Cited by
106References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Aug 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.