System and method for the capture and preservation of intermediate error state data
US7814374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Oct 12, 2010 |
| Priority date | — |
| Expiry date | Jun 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0778
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor chip system having the capability to capture and preserve intermediate machine error state data, wherein the system comprises a second level cache, wherein the second level cache is commonly interfaced with a primary and secondary processing core, and at least two primary error event registers, wherein each primary error event register is logically associated to a respective processing core. Further, at least two secondary error event registers, wherein each secondary error event register is logically associated to a respective processing core, and at least two sub-primary error accumulation registers, wherein each sub-primary error accumulation register is logically associated to a respective primary error event register and a secondary error event register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.