Segmented pillar layout for a high-voltage vertical transistor
US7816731B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2009 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Mar 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.