Memory cell layout structure with outer bitline

US7816740B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Theodore W. Houston · Richardson, US
• Xiaowei Deng · Plano, US

Key dates

• Filing date: Sep 12, 2008
• Grant date: Oct 19, 2010
• Expiry date: Jul 9, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor.