Inverting flip-flop for use in field programmable gate arrays
US7816946B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2009 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Jan 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1778
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.