Column selectable self-biasing virtual voltages for SRAM write assist
US7817481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2008 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Nov 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory decoder circuit includes a first cell supply line coupled to provide a first column of memory cells a first cell supply voltage and a second cell supply line coupled to provide a first column of memory cells a first cell supply voltage. The decoder circuit further includes a write assist circuit having a first threshold transistor coupled to the first cell supply line and a second threshold transistor coupled to the second cell supply line. In response to a write assist signal, the write assist circuit connects one of the first and second cell supply lines selected by control circuitry to an associated one of the first and second threshold transistors, such that a cell supply voltage of the selected one of the first and second cell supply lines is reduced toward the threshold voltage of the threshold transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.