Apparatus and method for avoiding steady-state oscillations in the generation of clock signals

US7817766B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Peter Gregorius · Munich, DE
• Thomas Rickes · Munich, DE
• Ralf-Rainer Schledz · St. Margarethen, AT
• Martin Streibl · Petershausen, DE

Key dates

• Filing date: Oct 30, 2006
• Grant date: Oct 19, 2010
• Expiry date: Aug 19, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/0816
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.