Method and apparatus for performing two's complement multiplication
US7818361B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Mar 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a novel way of performing a signed multiplication. Each individual bit of a first operand is multiplied by every bit of a second operand to generate partial multiplication results. Each partial result is shiftably added to other partial results except one partial result which is shiftably subtracted. For the partial result that is subtracted, the most significant bit of the second operand is negated and is utilized as carry in of the subtraction operation. The most significant bit of each operand is considered to have a negative sign when generating the partial multiplication results. Also, one of the partial results is appended with the most significant bit of the second operand. Some embodiments utilize a configurable IC that performs subtraction with the same circuitry and at the same cost as addition. The configurable IC also utilizes hybrid interconnect/logic circuits to perform part of the multiplication operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.