Arrangement and method for connecting a processing node in a distribution system
US7818613B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2004 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Jun 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An arrangement and method for interconnecting fail-uncontrolled processor nodes in a dependable distributed system. A node has a bus guardian with input switches which act in combination with a logic element as an input multiplexer under the control of a control unit.This provides the advantage of transferring the problem of fault containment from the output interface of a potentially faulty processing node to the input interface of fault-free processing nodes. By doing so, problems encountered by spatial proximity faults or functional dependencies within a faulty processing node that may jeopardize fault containment at its output interface are mitigated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.