Methodology for improving device performance prediction from effects of active area corner rounding
US7818693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2008 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Dec 21, 2028 |
Classification
- Technology area (CPC —)General
Abstract
A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.