Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores
US7818696B2 · kind B2 · utility
2Cited by
1References
4Claims
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Key dates
| Filing date | Jul 20, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Mar 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.