Ken V. Vu
36Patents
12h-index
52Co-inventors
84Inventor score
Filing activity: Nov 16, 1992 → Apr 29, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5426637A | Methods and apparatus for interconnecting local area networks with wide area backbone networks | Electricity | 241 | Expired |
| US5936940A | Adaptive rate-based congestion control in packet networks | Electricity | 138 | Expired |
| US5909443A | ATM network congestion control system using explicit rate cell marking | Electricity | 73 | Expired |
| US6075769A | Method and apparatus for network flow control | Emerging Cross-Sectional Technologies | 67 | Expired |
| US6633585B1 | Enhanced flow control in ATM edge switches | Electricity | 50 | Expired |
| US5398012A | Distributed processing of route selection across networks and subnetworks | Electricity | 49 | Expired |
| US5365523A | Forming and maintaining access groups at the lan/wan interface | Electricity | 43 | Expired |
| US6035333A | Method and system for providing congestion control in a data communications network | Electricity | 39 | Expired |
| US6400686B1 | Method and apparatus for network flow control | Emerging Cross-Sectional Technologies | 29 | Expired |
| US6587436B1 | Method and apparatus for allocation of available bandwidth | Electricity | 24 | Expired |
| US7103050B1 | Method and means for determining the used bandwidth on a connection | Electricity | 13 | Expired |
| US6359862B1 | ATM network available bit rate (ABR) explicit rate flow control system | Electricity | 12 | Expired |
| US8078852B2 | Predictors with adaptive prediction threshold | Physics | 12 | Active |
| US9378069B2 | Lock spin wait operation for multi-threaded applications in a multi-core computing environment | Physics | 9 | Active |
| US6185187A | Method and apparatus for relative rate marking switches | Electricity | 9 | Expired |
| US7453798B2 | Active flow management with hysteresis | Electricity | 9 | Expired |
| US8200905B2 | Effective prefetching with multiple processors and threads | Physics | 8 | Active |
| US9354884B2 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Physics | 6 | Active |
| US7249331B2 | Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores | Physics | 4 | Expired |
| US8543767B2 | Prefetching with multiple processors and threads via a coherency bus | Physics | 3 | Active |
| US6336167B1 | Cache storage management using dual stacks | Physics | 3 | Expired |
| US10114652B2 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Physics | 3 | Active |
| US7818696B2 | Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores | Physics | 2 | Active |
| US9841998B2 | Processor power optimization with response time assurance | Emerging Cross-Sectional Technologies | 2 | Active |
| US9948513B2 | Managing servers with quality of service assurances | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.