Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
US7818702B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Oct 19, 2010 |
| Priority date | — |
| Expiry date | Dec 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
Abstract
Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.