Method for fabricating semiconductor device
US7820537B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2009 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Nov 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/664
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming a polysilicon layer, a barrier metal layer, and a conductive layer over a substrate, forming gate hard masks over the conductive layer, etching the conductive layer and the barrier metal layer using the gate hard masks to form barrier metal electrodes and metal gate electrodes having a line width smaller than that of the gate hard masks, etching the polysilicon layer to form gate patterns, each gate pattern including a stack structure of a polysilicon electrode, the barrier metal electrode, the metal gate electrode, and the gate hard mask, forming a gate spacer over the surface profile of the substrate structure, forming an insulation layer over the gate spacer, etching the insulation layer to form a contact hole between the gate patterns and burying a conductive material over the contact hole to form a landing plug contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.