Power and ground routing of integrated circuit devices with improved IR drop and chip performance
US7821038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Sep 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.