Leadframe having delamination resistant die pad
US7821113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Jun 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18301
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413). A mold compound (414) encapsulates the integrated circuit (405), wherein the mold compound (414) is present inside the first plurality of grooves to form a restraint from delaminating between the m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.