Impedance calibration period setting circuit and semiconductor integrated circuit
US7821292B2 · kind B2 · utility
3Cited by
23References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2009 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Jun 29, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An impedance calibration period setting circuit includes a command decoder and an impedance calibration activation signal generator. The command decoder combines external signals to generate a refresh signal. The impedance calibration activation signal generator is configured to generate an impedance calibration activation signal in response to the refresh signal and an address signal. The impedance calibration period setting circuit prevents abnormal changes in an impedance calibration code and reduces current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.