Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors
US7821350B2 · kind B2 · utility
5Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.