Jeffrey Todd Bridges
57Patents
12h-index
58Co-inventors
87Inventor score
Filing activity: Aug 31, 1992 → Sep 12, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5996092A | System and method for tracing program execution within a processor before and after a triggering event | Physics | 81 | Expired |
| US6055584A | Processor local bus posted DMA FlyBy burst transfers | Physics | 70 | Expired |
| US6826747B1 | System and method for tracing program instructions before and after a trace triggering event within a processor | Physics | 63 | Expired |
| US6081860A | Address pipelining for data transfers | Physics | 50 | Expired |
| US5291076A | Decoder/comparator and method of operation | Electricity | 49 | Expired |
| US5450560A | Pointer for use with a buffer and method of operation | Physics | 39 | Expired |
| US5809293A | System and method for program execution tracing within an integrated processor | Physics | 36 | Expired |
| US7624256B2 | System and method wherein conditional instructions unconditionally provide output | Physics | 20 | Expired |
| US9413344B2 | Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems | Electricity | 17 | Active |
| US7152155B2 | System and method of correcting a branch misprediction | Physics | 17 | Expired |
| US6513134B1 | System and method for tracing program execution within a superscalar processor | Physics | 14 | Expired |
| US7278012B2 | Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions | Physics | 13 | Expired |
| US8008961B2 | Adaptive clock generators, systems, and methods | Electricity | 12 | Active |
| US7415638B2 | Pre-decode error handling via branch correction | Physics | 10 | Active |
| US8725488B2 | Method and apparatus for adaptive voltage scaling based on instruction usage | Emerging Cross-Sectional Technologies | 10 | Active |
| US7366869B2 | Method and system for optimizing translation lookaside buffer entries | Physics | 10 | Expired |
| US7587580B2 | Power efficient instruction prefetch mechanism | Physics | 8 | Expired |
| US7805588B2 | Caching memory attribute indicators with cached memory data field | Emerging Cross-Sectional Technologies | 7 | Active |
| US7426626B2 | TLB lock indicator | Physics | 7 | Active |
| US7366877B2 | Speculative instruction issue in a simultaneously multithreaded processor | Physics | 7 | Expired |
| US8797095B2 | Adaptive voltage scalers (AVS), systems, and related methods | Emerging Cross-Sectional Technologies | 6 | Active |
| US7421568B2 | Power saving methods and apparatus to selectively enable cache bits based on known processor state | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6948053B2 | Efficiently calculating a branch target address | Physics | 5 | Expired |
| US6816962B2 | Re-encoding illegal OP codes into a single illegal OP code to accommodate the extra bits associated with pre-decoded instructions | Physics | 5 | Expired |
| US7821350B2 | Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors | Electricity | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.