Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays
US7821834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Mar 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to be retrieved during read operations and a plurality of immediately adjacent non-addressable “dummy” memory cells configured to store dummy data that is not retrievable during the read operations. The plurality of dummy memory cells include at least one auxiliary dummy memory cell that operates as a buffer against lateral hole transfer within a charge trap layer of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.