eDRAM hierarchical differential sense AMP
US7821858B2 · kind B2 · utility
5Cited by
28References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2008 |
| Grant date | Oct 26, 2010 |
| Priority date | — |
| Expiry date | Dec 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.