Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design

US7823107B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Igor Arsovski · Williston, US
• Serafino Bueti · Waterbury, US
• Joseph A. Iadanza · South Burlington, US
• Jason M. Norman · South Burlington, US
• Hemen R. Shah · South Burlington, US
• Sebastian T. Ventrone · South Burlington, US

Key dates

• Filing date: Oct 19, 2007
• Grant date: Oct 26, 2010
• Expiry date: Dec 25, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/396
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.