Semiconductor memory

US7825439B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Tatsuo Izumi · Yokkaichi, JP
• Takeshi Kamigaichi · Yokohama, JP
• Shinya Takahashi · Hong Kong, CN

Key dates

• Filing date: Aug 14, 2008
• Grant date: Nov 2, 2010
• Expiry date: Nov 7, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.