Semiconductor die packages having overlapping dice, system using the same, and methods of making the same
US7825502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2008 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jul 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor die packages having overlapping dice, systems that use such packages, and methods of making such packages. An exemplary die package comprises a leadframe, a first semiconductor die, and a second semiconductor die that has a recessed portion in one of its surfaces. The first die is disposed over a first portion of the leadframe, and the second die is disposed over a second portion of the leadframe with its recess portion overlying at least a portion of the first die. Another exemplary die package comprises a leadframe with a recessed area, a first semiconductor die disposed in the recessed area, and a second semiconductor die overlying at least a portion of the first die. Preferably, electrically conductive regions of both dice are electrically coupled to a conductive region of the leadframe to provide an interconnection between dice that has very low parasitic capacitance and inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.