Receiver circuit having compensated offset voltage
US7825699B2 · kind B2 · utility
2Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jan 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45354
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.