Memory column redundancy scheme
US7826285B2 · kind B2 · utility
1Cited by
9References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Jul 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for implementing a memory column redundancy scheme is provided. The system comprises a core array having a plurality of columns and a redundancy column each configured for reading or writing a bit of information and circuitry for steering around a defective column in the core array, wherein the circuitry includes one column multiplexor, which results in having the memory column redundancy scheme include one multiplexing stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.