Testing non-volatile memory devices for charge leakage
US7826287B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2006 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Aug 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method of and apparatus for testing a floating gate non-volatile memory semiconductor device comprising an array of cells including floating gates for storing data in the form of electrical charge. The method includes applying a test pattern of said electrical charge to the floating gates, exposing the device to energy to accelerate leakage of the electrical charges out of the cells, and subsequently comparing the remaining electrical charges in the cells to the test pattern. The energy is applied in the form of electromagnetic radiation of a wavelength such as to excite the charges in the floating gates to an energy level sufficient for accelerating charge loss from the floating gates of defective cells relative to charge loss from non-defective cells. The wavelength is preferably in the range of 440 to 560 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.