Time-multiplexed routing for reducing pipelining registers
US7827433B1 · kind B1 · utility
10Cited by
24References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 16, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | May 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Serializing circuitry is provided that can multiplex multiple device output signals and that can drive time-multiplexed data signals on the bus wires of a data path of an electronic system. Bus registers placed at the ends of the bus wires can register or buffer the data signals transmitted over the bus wires. The registered signals may be passed on to deserializing circuitry for demultiplexing the data signals to provide parallel device input signals. The bus registers and the serializing/deserializing circuitry can be provided along signal paths that require additional latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.