Enhanced hardware debugging with embedded FPGAS in a hardware description language
US7827510B1 · kind B1 · utility
52Cited by
110References
45Claims
0Family size
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Key dates
| Filing date | May 31, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Dec 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.