Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs
US7827513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2007 |
| Grant date | Nov 2, 2010 |
| Priority date | — |
| Expiry date | Nov 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categorized and distinguished as either horizontal slots or vertical slots. Buffer to buffer data flow is reviewed for cases where data flow direction is either strongly horizontal or strongly vertical. Situations where buffer to buffer data flow is oriented in the same direction as the parent placement slots in which the buffers reside are reported. Additionally, an attempt is made to find a valid placement location for the buffers excluding parent placement areas oriented in the same direction as the data flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.