Wafer level stacked die packaging
US7829379B2 · kind B2 · utility
3Cited by
24References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Feb 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor devices by applying a pattern of adhesive pads on an active surface of a semiconductor wafer, the semiconductor wafer product so made and a stacked die package in which an adhesive wall leaves an air gap atop a bottom die. The wall may be in the form of a ring of adhesive about a central hollow area. The wafer carrying the pattern of adhesive pads on its active surface is singulated into individual dies, each die having an adhesive pad thereon. The bottom die is attached to a base with an adhesive which cures without curing the adhesive pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.