Lateral diffusion field effect transistor with asymmetric gate dielectric profile
US7829945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Feb 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/683
Abstract
A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.