Carrier structure embedded with semiconductor chips and method for manufacturing the same
US7829987B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Feb 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Carrier structure embedded with semiconductor chips and method for manufacturing the same are disclosed. The carrier structure comprises a metal plate and pluralities of semiconductor chips. An adhesive material is disposed on both surfaces of the metal plate, and pluralities of cavities are formed through the metal plate. The semiconductor chips are embedded in the cavities and mounted in the metal plate. The semiconductor chips each have an active surface on which pluralities of electrode pads are disposed. A built-up structure is formed on the surface of the carrier structure and the active surfaces of the semiconductor chips, which has pluralities of conductive vias therein to conduct the semiconductor chips, and has pads thereon. Besides, the metal plate has an etching cavity between the semiconductor chips, and the etching cavity is filled with the adhesive material. The present invention solves the problem of metal burrs being formed when cutting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.