High density row RAM for column parallel CMOS image sensors
US7830292B2 · kind B2 · utility
5Cited by
12References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 13, 2009 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Jan 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a single block of memory for storing signals processed by the ADCs. The ADCs process signals received from one group of columns of pixels and, at a different time, the ADCs process signals from another group of columns of pixels. While one of the signals processed from a column is being stored in a first memory bank, signals previously processed and stored in a second memory bank are being readout of the storage locations and provided downstream for further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.