Apparatus and method of generating clock signal of semiconductor memory
US7830999B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Sep 8, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus for generating a clock signal of a semiconductor memory includes a first shifting unit that outputs first shifting signals using at least one periodic signal, a control signal generating unit that outputs multiplexing control signals using an inverted clock signal, a second shifting unit that outputs second shifting signals using at least one of the periodic signals, a correcting unit that outputs correction signals having an intermediate phase between the phase of the first shifting signals and the phase of the second shifting signals on the basis of a bias signal applied thereto, a combination unit that combines the first shifting signals and the correction signals to output combined signals, a multiplexing unit that selectively outputs the combined signals on the basis of multiplexing control signals, and a driving unit that drives the clock signal and the inverted clock signal based on the output of the multiplexing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.