Histogram generation with configurable memory
US7831404B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 2007 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Sep 2, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The configuration and utilization of multiple memories is disclosed to efficiently gather histogram data for either multiple devices or single devices. Each memory can be configured depending on the number of ADCs to be tested. Rather than utilizing a separate histogram engine for each ADC, or duplicate memories to test each ADC, the memory of each histogram engine can be used either for a single ADC having a large or otherwise substantial sample width, or for multiple ADCs, each having a smaller sample width. To accomplish this, the memory is partitioned into multiple segments using address decoding such that a single ADC can use all of the segments for histogram data collection, while multiple ADCs can each use one of the segments for histogram data collection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.