Direct memory access-based multi-processor array
US7831801B1 · kind B1 · utility
52Cited by
12References
20Claims
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Key dates
| Filing date | Aug 30, 2006 |
| Grant date | Nov 9, 2010 |
| Priority date | — |
| Expiry date | Apr 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access (“DMA”)-based multi-processor array architecture that may be implemented in a single integrated circuit is described. The integrated circuit includes a plurality of processing units. A first processing unit and a second processing unit of the plurality of processing units are topologically coupled via a first DMA block. The first DMA block includes a first dual-ported random access memory and a first decoder. A multiple-processor array is provided by topologically coupling the first processing unit and the second processing unit via the first direct memory access block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.