Method for manufacturing resistance RAM device
US7833898B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2009 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | May 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
Abstract
Manufacturing a resistance RAM device includes the steps of forming an insulation layer on a semiconductor substrate having a bottom electrode contact; etching the insulation layer to define a hole exposing the bottom electrode contact; depositing sequentially a bottom electrode material layer and a TMO material layer selectively within the hole; depositing a top electrode material layer within the hole and on the insulation layer in such a way as to completely fill the hole in which the bottom electrode material layer and the TMO material layer are formed; removing partial thicknesses of the top electrode material layer and the insulation layer to form a stack pattern comprising a bottom electrode, a TMO, and a top electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.