Low voltage diode with reduced parasitic resistance and method for fabricating
US7834367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Jul 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
A method of making a diode begins by depositing an AlxGa1−xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an AlxGa1−xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au-Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal,; and an ohmic contact is deposited on the n+ layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.