Integrated circuit having a semiconductor arrangement
US7834427B2 · kind B2 · utility
0Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2007 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Apr 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.