Semiconductor memory device for generating column address
US7835204B2 · kind B2 · utility
4Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Oct 29, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device can ensure a sufficient margin between a column select signal and a column address signal when a delay time of the column select signal is increased to improve an address access time during a write operation. The semiconductor memory device includes a discrimination signal generating circuit configured to generate a discrimination signal activated in a write operation of the device, and a selective delay circuit configured to selectively delay a column address in response to the discrimination signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.