Write-assist and power-down circuit for low power SRAM applications
US7835217B1 · kind B1 · utility
13Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2009 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Aug 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.