Jason Su
41Patents
8h-index
18Co-inventors
72Inventor score
Filing activity: Mar 23, 1999 → Jul 8, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8418514B1 | Tablet protector | Emerging Cross-Sectional Technologies | 34 | Active |
| US7596012B1 | Write-assist and power-down circuit for low power SRAM applications | Physics | 23 | Active |
| US7639057B1 | Clock gater system | Physics | 20 | Active |
| US9032766B2 | Anti-theft mechanism for electronic devices | Emerging Cross-Sectional Technologies | 19 | Active |
| US8964452B2 | Programmable resistance-modulated write assist for a memory device | Physics | 16 | Active |
| US8310894B1 | Write-assist and power-down circuit for low power SRAM applications | Physics | 13 | Active |
| US7835217B1 | Write-assist and power-down circuit for low power SRAM applications | Physics | 13 | Active |
| US8164972B1 | Address decoder | Physics | 11 | Active |
| US9644402B1 | USB lock for electronic devices | Electricity | 8 | Active |
| US8582387B1 | Method and apparatus for supplying power to a static random access memory (SRAM) cell | Physics | 8 | Active |
| US8505344B2 | Rotatable lock for a portable electronic device | Emerging Cross-Sectional Technologies | 6 | Active |
| US8164363B1 | Aysmmetric sense-amp flip-flop | Electricity | 5 | Active |
| US6275435A | Bi-directional sense amplifier stage for memory datapath | Physics | 5 | Expired |
| US7848173B1 | Address decoder | Physics | 4 | Active |
| US7113301B2 | System and method for automated access of a network page | Emerging Cross-Sectional Technologies | 4 | Expired |
| US7855587B1 | Asymmetric sense-amp flip-flop | Electricity | 4 | Active |
| US10808431B2 | Lock for electronic devices | Fixed Constructions | 4 | Active |
| US9698531B2 | USB lock for electronic devices | Electricity | 3 | Active |
| US7965123B2 | High boosting-ratio/low-switching-delay level shifter | Electricity | 3 | Active |
| US8451041B2 | Charge-injection sense-amp logic | Electricity | 3 | Active |
| US6408264B1 | Switch level simulation with cross-coupled devices | Physics | 3 | Expired |
| US10944213B2 | USB combination lock for electronic devices | Electricity | 2 | Active |
| US8027218B2 | Processor instruction cache with dual-read modes | Emerging Cross-Sectional Technologies | 2 | Active |
| US8295110B2 | Processor instruction cache with dual-read modes | Emerging Cross-Sectional Technologies | 2 | Active |
| US9142286B2 | Integrated circuit memory device with read-disturb control | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.