Systems and methods for access violation management of secured memory
US7836269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2006 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Dec 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/53
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an idle state. The host memory interface can analyze authentication information obtained via an authentication component, and information regarding memory partition rights, to determine whether a command partition violation exists as to the command. If a violation exists, the host memory interface can prevent the improper command from executing in the memory, and can cause a different operation to occur thereby allowing the memory to be placed in a known state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.