Three operand instruction extension for X86 architecture
US7836278B2 · kind B2 · utility
5Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2007 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Jan 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.