Patent · US Active

Method and apparatus for recovering from system bus transaction errors

US7836328B1 · kind B1 · utility

7Cited by
4References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 4, 2006
Grant dateNov 16, 2010
Priority date
Expiry dateJul 7, 2028

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F11/0745
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A method and apparatus for recovering from errors occurring during system bus transactions. An input/output device such as a network interface unit (NIU) issues read and write operations across a meta interface coupling the device to host bus (glue) logic. The host bus logic translates the operations into system bus transactions. The device maintains a set of reusable identifiers for identifying the operations, and a table maintained by the device or the host bus logic maps the operation identifiers to transaction identifiers identifying the system bus transactions spawned to perform the operations. If a bus transaction encounters an unrecoverable error, the host bus logic reports the error to the device and drops any further data received from other bus transactions performed for the same operation. The device marks the operation's identifier as dirty, to prevent its reuse. The operation identifier may be reused after software clears the error condition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.